基于MATALB的数据采集器设计外文原文

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'基于MATALB的数据采集器设计外文原文'
First Experience with the Scalable Coherent InterfaceH.MullerECP Division, CERN, CH 1211 Geneva 23SwitzerlandandA.Bogaerts1、 J.Buytaert1,R.Divia [ A.Ivanov2, R.Keyser1, F.Lozano-Alemany2. IHEP Protvino, Russia,GMugnai1, D.Samyn1 ,B.Skaali University of OSLO, Physics Department, NorwayRD24 Collaboration, CERN, CH 1211 Geneva 23, SwitzerlandAbstractThe research project RD24 [11] is studying applications of the Scalable Coherent Interface (IEEE-1596) standard for the large hadron collider (LHC). First SCI node chips from Dolphin were used to demonstrate the use and functioning of SCFs packet protocols and to measure data rates. We present results from a first,two-node SCI ringlet at CERN, based on a R3000 RISC processor node and DMA node on a MC68040 processor bus. A diagnostic link analyzer monitors the SCI packet protocols up to full link bandwidth. In its second phase, RD24 will build a first implementation of a multi-ringlet SCI data merge匚I. BASICS of SCI1. CERN, Geneva Switzerland3. Universidad Politecnica de Madrid, SpainSCI [1] provides bus like features between SCI nodes in a ringlet. Point-to-point links interconnect the inputs and outputs of SCI nodes (fig 1). These transmit incoming packets either to the output link, or direct them into an input FIFO. Packets which are generated by user-logic on the Cbus [2] side are queued in an output FIFO until the bypass FIFO is empty. In this way, several nodes in a ringlet may be receiving and transmitting simultaneously at the intrinsic node-chip speed to achieve a ringlet bandwidth which is significantly higher than the node chip bandwidth SCI links transport packets as shown schematically in fig 2. A flag signal delimits packets which are composed of data or control symbols, clocked at every transition of the SCI clock. The 16 bit wide link of a GaAS NodeChip? [3] from Dolphin transmits one 16 bit symbol every 2 ns, resulting in a raw link bandwidth of 1 Gbyte/s. SCI packets are framed by a header, containing address and command fields, and a CRC traile匚 Transactions consist of two subactions: during the request subaction a packet containing address, command and optionally data is sent to a responder node. After it's intrinsic latency, the responder starts the response subaction, which in case of a read transaction returns data via a response packet. Typical transactions, implemented in the first node chips are: read/write cached or noncached 64 byte, read/write 1 to 16 byte noncached, and move 64 byte transactions. SCI uses 64 bit addresses. The upper 16 bits specify the node-identifier within a 64K node address space. FLAGI6xDAlAPACKE1 s2ns{5tiU MHz)16 bit DATA *2ns= 1 GB sCRCDA1A16. 64. 256 bytesHEADERADDRESS (64 bits) 一 COMMANDFigure 2: Signals and PacketsThe remaining 48 bits are the internal byte address in that node. SCI complies fully with the IEEE 1212 CSR standard [4].II. A PREVIEW of SCI for DATA ACQUISITIONData acquisiti
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基于 MATALB 数据 采集 设计 外文 原文
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